1. Field of the Invention
This invention relates to a dividing apparatus and, more particularly, to a high-speed dividing apparatus for electronic digital computers.
2. Description of Related Art
A carry save adder (CSA) is distinguished from other types of adders by the fact that the carry bits and half-sum bits which result from each addition are not immediately combined or consolidated but instead are saved separately from each other for subsequent use in the next addition performed by the CSA, the inputs to which comprise the saved carry and half-sum bits (the latter hereinafter referred to simply as "sum bits" for convenience) and the bits of an operand which is being added to, or in some instances being effectively substracted from, the value jointly represented by these saved carry and sum bits.
Carry save adders commonly are employed in high-speed multipliers, where they generally are able to function more rapidly than "carry propagate" or "ripple carry" adders because a carry save adder does not completely perform the relatively time-consuming process of combining carries with sum bits between successive additions in the multiplication process but instead defers this task until the final cycle of the multiplying operation. It has been proposed also to use a carry save adder in dividing operations, as disclosed in U.S. Pat. No. 4,084,254 to R. E. Birney et al, the advantage of this proposal being that it enables a combination multiplier-divider unit to be provided with a single adder of the CSA type for use in both multiplying and dividing operations.
As they generally are employed, carry save adders have a disadvantage that has detracted from their utility despite the above-described speed advantage which they offer. There are many instances during the performance of adding, complementing and column shifting functions where a carry or sum bit manifested at the output side of any order or bit position in the adder must be re-entered as input to that same order or bit position in the adder. Because of this re-entrancy requirement, it has been customary to provide carry save adders in duplicate and operate the pair of adders in alternation so that an output bit from any order or position in one adder of the pair may, if necessary, be applied as input to the corresponding order or position in the other adder of the pair, without thereby causing an undesirable interaction between an output bit and its re-entered counterpart at the same CSA bit position. This duplication of adder equipment introduces a cost consideration which must be weighed against the speed consideration in a conventional CSA installation. While it is desirable to eliminate the use of duplicate adder equipment and employ a single CSA having only one ordered set of bit positions for achieving the results described above, this must be accomplished without impairing the ability of the CSA to perform all of the functions required of it. In particular, some way must be provided for handling the re-entrancy problem where there is no duplicate set of CSA bit positions available for that purpose.
Where a carry save adder is being used as part of a divider apparatus, as proposed in the aforesaid Birney et al. patent, there is an additional requirement that the CSA must provide information that can be used in a lookahead logic network to determine beforehand from the various CSA output values whether or not each proposed complemental subtraction in the division process may be successfully performed without causing an overdraft. For this purpose each CSA bit position must provide two types of output bits: (1) latched sum and carry output bits which can be set or changed only at predetermined clock times, being stable at all other times; and (2) unlatched sum and carry bits (hereinafter referred to as "presum" and "precarry" bits), whose respective values at every instant will be determined by the instantaneous values of the current inputs to that CSA bit position, the latter being used in making the trial determinations to prevent the occurrence of overdrafts. The conventional carry save adder cannot provide both latched and unlatched outputs from the same bit cell.
In the course of normal operation, a digital computer performs numerous calculations including addition, subtraction, multiplication, and division. Division is, by far, the most complex of these operations, typically requiring more hardware and computational time than the other operations. The prior art provides a variety of division techniques, which have in common the utilization of an interative method for quotient production. The iterative method generally involves generating a single quotient digit in each iterative cycle. Three of the prior art techniques are discussed below.
A restoring division technique is characterized by the selection of quotient digits in the range 0, 1, . . . , (beta-1); where beta is the radix of the division. Thornton, Design of a Computer-The Control Data 6600, (Scott, Foresman and Co., Glenview, Ill., 1970, pp. 101-105) discloses a radix-4 divider employing this division technique. The apparatus incorporates three adder/subtractor units for the simultaneous calculation of candidate divisor multiples and operates according to a method similar to that of manual, pencil-and-paper division.
A second division technique, non-restoring division, is characterized by the selection of quotient digits having the values-(beta-1), . . . , -2, -1, 1, 2, . . . , (beta-1). A procedure employing a modified form of this technique is discussed by Nandi et al. in "A Simple Technique for Digital Division" (Communications of the ACM, No. 10, 1967, pp. 299-301). In the quotient digit-producing iterative phase, the Nandi et al. method generates successive "partial remainders," values reflecting the difference between the numerator and the multiplicative product of the denominator and the previously generated quotient digits. Within the iterative phase, a single radix-beta quotient digit is generated as a mathematical function of each partial remainder.
A variant of the non-restoring division technique is provided by SRT division, which is also characterized by the selection of quotient digits in the range-(beta-1), . . . , -1, 0, 1, . . . , (beta-1). A discussion of the SRT technique is provided by Robertson, "A New Class of Digital Division Methods," IRE Transactions on Electronic Computers, vol. EC-7, pp. 218-222, September, 1958. The Robertson method employs an iterative process similar to that used by the Nandi et al. However, in Robertson, each quotient digit is generated by operation of a selection circuit, which incorporates a large look-up table.
Drawbacks presented by the prior division methods are numerous. In Thornton, for example, the performance increases do not offset the costs associated with the increased hardware requirements. Both Robertson and Nandi et al. generate quotient digits in a manner which requires increased hardware in order to achieve conversion of individual quotient digits to a conventional, restoring form. Nandi et al., further, requires examination, in some cases, of two leading radix-beta digits of a partial remainder in order to produce a single quotient digit. Moreover, the Robertson method requires a look-up table having a size which rapidly increases as a function of increased radix. Further, this method requires a large data path length, i.e., the bit-wise length of signals transferred between divider elements.